The present invention relates to nonvolatile memories.
FIG. 1 shows a cross section of a flash memory cell described in U.S. Pat. No. 6,057,575 issued May 2, 2000 to Jenq. The cell is formed in and over a semiconductor substrate 120. Silicon dioxide 130 is thermally grown on substrate 120. Select gate 140 is formed on oxide 130. Silicon dioxide 150 is thermally grown on a region of substrate 120 not covered by the select gate. ONO 154 (a sandwich of a layer of silicon dioxide, a layer of silicon nitride, and a layer of silicon dioxide) is formed on select gate 140. Floating gate 160 is formed on dielectric layers 150, 154. A portion of floating gate 160 overlies the select gate 140.
ONO layer 164 is formed on the floating and select gates. Control gate 170 is formed on ONO 164. The control gate overlies floating gate 160 and select gate 140.
N+ source and drain regions 174, 178 are formed in substrate 120.
The cell is programmed by hot electron injection from the cell's channel region 180 (a P type region of substrate 120) to floating gate 160. The cell is erased by Fowler-Nordheim tunneling of electrons from floating gate 160 to source region 178.
The cell is fabricated by a self-aligned process in which the left and right edges of floating gate 160 and control gate 170 are defined by a single mask.
Another self-aligned fabrication process is described in Naruke et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on Its Source Side”, IEDM Technical Digest 1989, pages 603-606. In that process, the floating and control gates are formed first in a stacked configuration. Then the select gate is formed as a sidewall spacer on a sidewall of a structure including the floating and control gates.